Gate-All-Around Transistors at 3nm: Device Physics, Fabrication Challenges, and Beyond FinFET Scaling

Abstract

This paper provides a comprehensive review of Gate-All-Around (GAA) transistors at the 3nm technology node, a critical inflection point in the semiconductor industry. While Moore's Law, as an empirical observation of exponential transistor scaling, faces fundamental physical and economic limits, the industry continues to advance through architectural innovation. The report first traces the evolution from planar to three-dimensional (3D) FinFETs, highlighting how the latter's scaling limitations at sub-5nm dimensions necessitated a new paradigm. It then delves into the superior device physics of GAA transistors, which achieve enhanced electrostatic control by fully wrapping the channel, thereby mitigating severe short-channel effects and quantum phenomena that degrade FinFET performance. A detailed analysis of the engineering challenges including advanced EUV lithography, complex inner spacer fabrication, and nanosheet stacking variability, is presented. The paper also provides a comparative review of the divergent strategies of leading foundries: Samsung's early, high-risk transition to GAAFETs at 3nm versus TSMC's decision to push its refined FinFET architecture to its absolute limit. Finally, it explores the roadmap beyond 3nm, examining emerging architectures like Complementary FETs (CFETs), the potential of novel two-dimensional (2D) materials as a replacement for silicon, and the profound influence of artificial intelligence (AI) and machine learning (ML) workloads in driving system-level, rather than purely transistor-level, innovation.